Processors in multiprocessing systems typically utilize a hierarchy of caches to speed access to data stored in a main memory of the system. The first level of such a hierarchy usually is a small, fast primary (L1) cache that may be integral to the processor. Upper levels of cache memory commonly are shared among the processors. The processors typically arbitrate for access to a shared second-level (L2) cache memory in which a tag array and a data array are stored. A central arbiter, for example, a cache controller driven by arbitration logic, determines the order in which the processors gain access to the L2 cache. The cache controller utilizes the L2 tag array to access data held in the L2 data array and transmits the data to a requesting processor.
Because processor accesses to the L2 cache typically are serialized, system performance can be slowed during times when more than one processor makes intensive use of the L2 cache. One alternative would be to provide multiple ports to the L2 cache tag array so that more than one processor at a time could retrieve data, but such systems can be prohibitively expensive.